As Q and Q are always different we can use them to control the input. If the circuit is “RESET” the K input is inhibited by the “0” status of Q through the upper NAND gate. If the circuit is now “SET” the J input is inhibited by the “0” status of Q through the lower NAND gate. The difference this time is that the “JK flip flop” has no invalid or forbidden input states of the SR Latch even when S and R are both at logic “1”. The sequential operation of the JK flip flop is exactly the same as for the previous SR flip-flop with the same “Set” and “Reset” inputs. The two inputs labelled “J” and “K” are not shortened abbreviated letters of other words, such as “S” for Set and “R” for Reset, but are themselves autonomous letters chosen by its inventor Jack Kilby to distinguish the flip-flop design from other types. This simple JK flip Flop is the most widely used of all the flip-flop designs and is considered to be a universal flip-flop circuit. Then to overcome these two fundamental design problems with the SR flip-flop design, the JK flip Flop was developed. if Set or Reset change state while the enable (EN) input is high the correct latching action may not occur the Set = 0 and Reset = 0 condition (S = R = 0) must always be avoided Unlike the JK Flip-flop, the basic S-R NAND flip-flop circuit has many advantages and uses in sequential logic circuits but it suffers from two basic switching problems.
